2026-08-04 03:46 UTC
Replies (2)
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@brouhaha@mastodon.social 2026-08-04 04:10
@hanshuebner@mastodon.social @me_@sueden.social Without looking, probably to interface the J11 bus to the entirely dissimilar Apple II bus, do address decode, and perhaps to support on-card memory. At least, that's what I've done for my own Apple II projects, and my own J11 projects. Otherwise it would likely take too many chips to fit on an Apple II card.
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@me_@sueden.social 2026-08-04 06:31
@hanshuebner@mastodon.social I think @brouhaha@mastodon.social had the right idea. The SystemVerilog source file included mentions a "DCJ11 TangNano interface by nanja.info [...] PSRAM interface module [...] 4MB RAM" in ram.sv. The top.sv module is connected to: DAL, BS, AIO (J11 side, data/addresses multiplexed) and Apple II Data D, Apple II /IOSEL, Apple II R/W plus the PSRAM. There also seems to be peripheral emulation (or addr. decoding) for a DLART and a PC11. Now where do I find a J11 module? 😀