@sven @janne USB2 is kind of a massive thorn in the side of Type-C handling tbf >_< On Qualcomm SoCs we have a fun issue: the USB2 PHY derives its clock from the USB3 PIPE clock, and the QMPPHY driver currently turns PIPE off when you go into 4-lane alt mode, so using 4-lane DP breaks USB2 on that port until full reboot :D (and just Not Turning it Off only fixes hotplugged devices, I'm gonna try modeling the clk relationship properly) But hey, at least that's literally our only issue and we don't ever have to reset anything :P